Electrically erasable programmable logic device

US6617637B1 · kind B1 · utility

Assignee

• EMEMORY TECHNOLOGY INC. · TW

Inventors

• Ching-Hsiang Hsu · Hsinchu, TW
• Yen-Tai Lin · Baoshan, TW
• Chih-Hsun Chu · Hsinchu, TW
• Shih-Jye Shen · Baoshan, TW
• Ching-Sung Yang · Hsinchu, TW
• Ming-Chou Ho · Taichung, TW

Key dates

• Filing date: Nov 13, 2002
• Grant date: Sep 9, 2003
• Expiry date: Nov 13, 2022

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2216/10

Abstract

An electrically erasable programmable logic device (EEPLD) includes a P type semiconductor substrate. An N type well is formed on the P type semiconductor substrate. A first PMOS transistor is formed on the N well. The first PMOS transistor comprises a floating gate, a first P+ doped region serving as a drain of the first PMOS transistor, and a P− doped region encompassing an N+ doped region for erasing the first PMOS transistor. A second PMOS transistor is also formed on the N well and serially connected to the first PMOS transistor. The first P+ doped region functions as a source of the second PMOS transistor, and the second PMOS transistor further comprises a select gate and a second P+ doped region serving as a drain of the second PMOS transistor.