Low power tunneling metal-oxide-semiconductor (MOS) device
US6617643B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 28, 2002 |
| Grant date | Sep 9, 2003 |
| Priority date | — |
| Expiry date | Jun 28, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D8/70
Abstract
A three terminal tunneling device that has a smaller voltage transition between off-current and on-current states and which also has less dependence on the lateral dimensions of the device. The device is a hybrid between a MOS transistor, a gated diode and a tunneling diode. The semiconductor device includes a lightly doped substrate of a first conductivity type. The lightly doped substrate will include a first heavily doped region of a first conductivity type formed in the substrate and a lightly doped layer of a first conductivity type disposed on the substrate and the first heavily doped region. The device also including a gate insulator layer disposed on the lightly doped layer and underlying a portion of the first heavily doped region and a gate electrode that is disposed on the gate insulator layer. Additionally, the device will include a second heavily doped region of a first conductivity formed in the substrate extending into the first heavily doped region of a first conductivity and a heavily doped region of a second conductivity formed in the substrate extending into the lightly doped substrate and spatially isolated from the first heavily doped region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.