Digital variable clock divider
US6617893B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1998 |
| Grant date | Sep 9, 2003 |
| Priority date | — |
| Expiry date | Mar 31, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/68
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock divider circuit and methods of operating same includes a standard integral clock divider circuit and a phase slip non-integral divider circuit for high granularity non-integral clock division. A multi-phase frequency synthesizer produces a plurality of phases of a clock frequency and applies the multiple phases to the divider circuit of the present invention. In a first embodiment, each phase is applied to a phase slip divider circuit which includes a integral divider portion and a programmable phase slip divider portion which receives the output of the integral division portion. Each phase of the input clock may therefore be divided by a wide variety of integral and non-integral divisors. In a second, simpler embodiment, a multi-phase frequency synthesizer produces a plurality of phases and applies the phases to a single phase slip divider. The single phase slip divider of the second embodiment may be configured to stay or shift on each phase of the clock in that consecutive phases may be merged or may remain distinct in the output signal of the phase slip non-integral divider portion of the circuit. The output of the phase slip divider of the second embodiment is then app…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.