Parallel plate buried capacitor
US6618238B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 25, 1999 |
| Grant date | Sep 9, 2003 |
| Priority date | — |
| Expiry date | Mar 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09672
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A novel capacitor foil and printed circuit board intermediate made using that foil are disclosed. The capacitor foil is a three-layer construction having a conductive layer, a partially-cured high dielectric constant layer, and a partially-cured bonding layer. The high dielectric constant and bonding layers are formed with epoxy or other polymer, however, the high dielectric constant layer is loaded with capacitive ceramic particles or pre-fired ceramic forming particles. The bonding layer may or may not be filled with ceramic particles or prefired ceramic-forming particles. The resulting capacitor foil may be applied to a laminate having copper patterns thereon to define a PCB intermediate containing at least one buried capacitor device. Multiple layers of capacitance material also can be used to increase the overall capacitance of the board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.