Adjustable memory self-timing circuit
US6618309B2 · kind B2 · utility
4Cited by
8References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2001 |
| Grant date | Sep 9, 2003 |
| Priority date | — |
| Expiry date | Oct 31, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static Random Access Memory (RAM) has a sense enable circuit. A user-determinable number of timing cells produces a timing bit line output in response to a wordline enable input. A sense timing control circuit is triggered by the timing bit line output. The sense timing control circuit produces a sense enable signal for enabling a sensing amplifier to read the logic state of memory cells in communication with the sensing amplifier. A user can change the number of timing cells to optimize operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.