System and method for parallel testing of IEEE 1149.1 compliant integrated circuits
US6618827B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 13, 2000 |
| Grant date | Sep 9, 2003 |
| Priority date | — |
| Expiry date | Apr 13, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318552
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention is generally related to a system and method for conducting parallel testing of IEEE1149.1 compliant integrated circuits hardware via comparing results generated by integrated circuits under evaluation in accordance with IEEE1149.1 JTAG/IEEE standard test access port and boundary scan architecture provisions, with a master reference signal to determine whether the integrated circuit is functioning properly. There is provided a multi-input scan chain select unit for receiving a selected group of integrated circuit test data inputs. There is provided a comparator unit for comparing each of the selected integrated circuit test data inputs with a predetermined reference signal and determining whether they are the same or not. Malfunctioning integrated circuits are identified based upon results of the comparison.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.