Method of forming a planar polymer transistor using substrate bonding techniques
US6620657B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2002 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Jan 15, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K10/466
Abstract
A structure and method of forming a fully planarized polymer thin-film transistor by using a first planar carrier to process a first portion of the device including gate, source, drain and body elements. Preferably, the thin-film transistors made with all organic materials. The gate dielectric can be a high-k polymer to boost the device performance. Then, the partially-finished device structures are flipped upside-down and transferred to a second planar carrier. A layer of wax or photo-sensitive organic material is then applied, and can be used as the temporary glue. The device, including its body area, is then defined by an etching process. Contacts to the devices are formed by conductive material deposition and chemical-mechanical polish.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.