Method to integrate high performance 1T ram in a CMOS process using asymmetric structure
US6620679B1 · kind B1 · utility
33Cited by
4References
89Claims
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Key dates
| Filing date | Aug 20, 2002 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Aug 20, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
Abstract
A high performance 1T RAM cell in a system-on-a-chip is formed using an asymmetric LDD structure that improves pass gate performance and storage node junction leakage. The asymmetric LDD structure is formed using selective ion implantation of the core and I/O LDDs. The node junctions are both pocket implant-free and source/drain implant-free. Further, silicide formation is avoided within the storage node junctions by forming nearly merged sidewall spacers within the node junctions and by forming optional blocking portions over the nearly merged sidewall spacers.
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