Twin-bit memory cell having shared word lines and shared bit-line contacts for electrically erasable and programmable read-only memory (EEPROM) and method of manufacturing the same
US6620683B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2001 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Dec 4, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28167
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor EEPROM device and a method for making it are achieved. The EEPROM device is a novel twin-bit cell structure with adjacent floating gates having a common control gate and common bit-line contact in each cell area. In each cell area a first and second floating gate is formed. Source areas are formed in the substrate adjacent to the outer edges of the floating gates and a drain area is formed between and adjacent to the floating gates. A gate oxide is formed over the floating gates. A control gate is formed over the drain area and patterned to also partially extend over the floating gates. The control gate is also patterned to provide a recess for a bit-line contact to the drain area. The recess results in reduced cell area and the non-critical overlay of the control gate over the floating gates results in relaxed overlay alignment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.