Zener-like trim device in polysilicon
US6621138B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 21, 2002 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Oct 21, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a polysilicon layer in which a first region of a first conductivity type and a second region of a second conductivity type is formed. The first region and the second region form a p-n junction in the polysilicon layer. The semiconductor device further includes a first metallization region in electrical contact with the first region and a second metallization region in electrical contact with the second region. In operation, a low resistance path is formed between the first and second metallization region when a voltage or a current exceeding a predetermined threshold level is applied to the first or the second region. The voltage or current is applied for zap trimming of the p-n junction where the voltage or current exceeding a predetermined threshold level, together with the resulting current or resulting voltage, provides power sufficient to cause the low resistance path to be formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.