Semiconductor apparatus having stress cushioning layer
US6621154B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2000 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Sep 28, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/09701
- WIPO fieldMacromolecular chemistry, polymers
- WIPO sectorChemistry
Abstract
A miniature semiconductor apparatus is outstanding in reflow resistance, temperature cycle property, and PCT resistance corresponding to high density packing, high densification, and speeding up of processing. The semiconductor apparatus has at least one stress cushioning layer on a semiconductor element with an electrode pad formed, having a conductor on the stress cushioning layer, having a conductor for conducting the electrode pad and conductor via a through hole passing through the stress cushioning layer between the electrode pad and the conductor, having an external electrode on the conductor, and having a stress cushioning layer in an area other than the area where the external electrode exists and a conductor protection layer on the conductor, wherein the stress cushioning layer includes crosslinking acrylonitrile-butadiene rubber having an epoxy resin which is solid at 25° C. and a carboxyl group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.