Semiconductor device having stacked multi chip module structure
US6621156B2 · kind B2 · utility
15Cited by
6References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 24, 2002 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Jan 24, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device in which a plurality of semiconductor chips are stacked. The semiconductor device includes a lower semiconductor chip bonded onto a surface of a wiring substrate; an upper semiconductor chip; and one or more spacers which are bonded to the surface of the wiring substrate and which support the upper chip over the lower chip and at a location separated from the lower chip. Conductors electrically connect the lower chip to the wiring substrate and extend through the spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.