Clocking and synchronization circuitry
US6621304B2 · kind B2 · utility
2Cited by
7References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 4, 2002 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Apr 4, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00247
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clocking and synchronization circuitry is disclosed. A plurality of windows is provided to accommodate jitters in a clock with respect to a reference clock. A plurality of delayed state cycles is generated from the clock signal for clocking internal operations within the clocked integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.