Partial swing low power CMOS logic circuits
US6621305B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2001 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Sep 6, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A logic gate circuit and related methods and apparatus exhibit reduced voltage swing and thereby consume less power. The circuit is connected to a plurality of input signals and a clock signal. The circuit produces an output. The circuit comprises a node, a pull-down network and an N-type MOS transistor. The pull-down network is connected to the node, a first reference voltage, the plurality of inputs and the clock signal. The N-type MOS transistor is connected between the node and a second reference voltage. The N-type MOS transistor is also connected to a complement of the clock signal. A method of the invention accepts a complement of a clock signal and pre-charges a node to a voltage less than a power supply voltage, in response to the complement of the clock signal. The method also accepts a plurality of input signals and accepts the clock signal. The method conditionally discharges the node, in response to the clock signal, on the basis of the plurality of input signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.