Frequency-compensated, multistage amplifier configuration and method for operating a frequency-compensated amplifier configuration
US6621334B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2002 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Dec 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/086
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency compensation circuit includes a first and a second compensation capacitor for a frequency-compensated amplifier to which a chopped useful signal can be supplied. In a first clock phase, the useful signal is respectively supplied to the first compensation capacitor, and in a second clock phase the useful signal is respectively supplied to the second compensation capacitor. As a result, a stable, frequency-compensated amplifier is specified in which charge reversal in the frequency compensation capacitors or Miller capacitors is avoided, making possible a configuration with a small chip area. The principle is suited particularly to Hall sensors operated in chopped mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.