Row decoder circuit for use in programming a memory device
US6621745B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 18, 2002 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Jun 18, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A row decoder circuit for use in programming a memory device. The row decoder circuit includes a means for selecting the wordline of a memory cell to be programmed and a wordline driver circuit that switches between a first power supply line that supplies a programming voltage and a second power supply line that supplies a read/verify voltage in order to provide either the programming voltage or the read/verify voltage to the gate of a selected memory cell on the wordline. This switching between programming and read/verify voltages results in the programming pulses used to program the selected memory cell. The present invention allows for shorter programming pulses to be used and provides faster speed in the overall programming of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.