Compact integrated circuit with memory array
US6621756B2 · kind B2 · utility
5Cited by
4References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2001 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Nov 26, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A compact integrated circuit with memory arrays, shared select transistors and distributed drivers of XDEC is disclosed. The shared select transistors are used to access two adjacent memory cell areas so that the overhead resulting from the conventional select areas can be reduced. The drivers of XDEC are distributed to both sides of the memory arrays to drive the memory cell areas so that conventional transfer areas can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.