Edge placement and jitter measurement for electronic elements
US6622107B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 25, 2000 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | May 3, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31937
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An apparatus compares propagation delay of electronic by using flip-flops or similar storage elements. The apparatus includes a strobe source having an output line coupled to a control terminal of a pattern source and an input terminal of a variable clock delay. The strobe source triggers the pattern source to output signal a sequence of signals to an input terminal of an element or device under test (DUT). The DUT propagates the signals to a flip-flop. The output signal of the flip-flop is captured after a delay. The propagation delay of the DUT is determined by coinciding the clock signal edge with the data signal edge to the flip-flop so that the flip-flop enters the ambiguity region. Once the delay settings that define the ambiguity region under the same delay are determined for various DUTs, they are compared to determine which DUT has the least propagation delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.