Virtual set cache that redirects store data to correct virtual set to avoid virtual set store miss penalty
US6622211B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2001 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Apr 17, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A virtual set cache that avoids virtual set store miss penalty. During a query pass of a store operation, only the untranslated physical address bits of the store address are used to index the cache array. In one embodiment, the untranslated physical address bits select four virtual sets of cache lines. In parallel with the selection of the four virtual sets, a TLB translates the virtual portion of the store address to a physical address. Comparators compare the tags of all of the virtual sets with the translated physical address to determine if a match occurred. If a match occurs for any of the four virtual sets, even if not the set specified by the original virtual address bits of the store address, the cache indicates a hit. The matching virtual set, way and status are saved and used during the update pass to store the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.