Rodney E. Hooker
141Patents
18h-index
24Co-inventors
86Inventor score
Filing activity: May 18, 1999 → Oct 7, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6832296B2 | Microprocessor with repeat prefetch instruction | Physics | 109 | Expired |
| US7546446B2 | Selective interrupt suppression | Physics | 65 | Expired |
| US6647489B1 | Compare branch instruction pairing within a single integer pipeline | Physics | 49 | Expired |
| US6338136B1 | Pairing of load-ALU-store with conditional branch | Physics | 48 | Expired |
| US6681311B2 | Translation lookaside buffer that caches memory type information | Physics | 43 | Expired |
| US9811468B2 | Set associative cache memory with heterogeneous replacement policy | Emerging Cross-Sectional Technologies | 37 | Active |
| US7191320B2 | Apparatus and method for performing a detached load operation in a pipeline microprocessor | Physics | 34 | Expired |
| US7065632B1 | Method and apparatus for speculatively forwarding storehit data in a hierarchical manner | Physics | 32 | Expired |
| US6549985B1 | Method and apparatus for resolving additional load misses and page table walks under orthogonal stalls in a single pipeline processor | Physics | 29 | Expired |
| US7181596B2 | Apparatus and method for extending a microprocessor instruction set | Physics | 28 | Expired |
| US9389863B2 | Processor that performs approximate computing instructions | Physics | 28 | Active |
| US6622211B2 | Virtual set cache that redirects store data to correct virtual set to avoid virtual set store miss penalty | Physics | 24 | Expired |
| US8364902B2 | Microprocessor with repeat prefetch indirect instruction | Physics | 23 | Active |
| US7111125B2 | Apparatus and method for renaming a data block within a cache | Physics | 22 | Expired |
| US8090931B2 | Microprocessor with fused store address/store data microinstruction | Physics | 22 | Active |
| US6810466B2 | Microprocessor and method for performing selective prefetch based on bus activity level | Physics | 22 | Expired |
| US8782348B2 | Microprocessor cache line evict array | Physics | 20 | Active |
| US9043580B2 | Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA) | Physics | 19 | Active |
| US7529912B2 | Apparatus and method for instruction-level specification of floating point format | Physics | 18 | Expired |
| US7315921B2 | Apparatus and method for selective memory attribute control | Physics | 17 | Expired |
| US7543134B2 | Apparatus and method for extending a microprocessor instruction set | Physics | 16 | Active |
| US7373483B2 | Mechanism for extending the number of registers in a microprocessor | Physics | 16 | Expired |
| US6553473B1 | Byte-wise tracking on write allocate | Physics | 16 | Expired |
| US8392693B2 | Fast REP STOS using grabline operations | Physics | 13 | Active |
| US6985999B2 | Microprocessor and method for utilizing disparity between bus clock and core clock frequencies to prioritize cache line fill bus access requests | Physics | 12 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.