Method and apparatus for pre-branch instruction
US6622240B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2000 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Feb 1, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus that minimizes instruction gaps behind a branch instruction in a multistage pipelined processor is disclosed. A pre-branch instruction that corresponds to a branch instruction to inserted into the instruction stream a sufficient number of instructions ahead of the branch instruction to insure that the pre-branch instruction exits the decode stage of the pipeline at the same time the branch instruction exits the first instruction fetch stage of the pipeline. The pre-branch instruction is decoded and causes the instruction fetch unit either to begin fetching instructions at a target address, where the branch is known or predicted to be taken, or to continue fetching instructions along the main execution path, the branch is known or predicted to be not taken.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.