Scan latch circuit
US6622273B1 · kind B1 · utility
23Cited by
8References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 11, 2000 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Apr 11, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A circuit is described which allows a scan latch to selectively pass inputs derived from either of two test outputs, e.g. scan test and built-in self-test data, but which does not apply an added delay to a data path when this is instead selected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.