Method of micro-architectural implementation on bist fronted state machine utilizing ‘death logic’ state transition for area minimization

US6622274B1 · kind B1 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Weng Fook Lee · Bukit Mertajam, MY
• Colin S. Bill · Cupertino, US
• Feng Pan · Kunshan, CN
• Edward V. Bautista, Jr. · Santa Clara, US

Key dates

• Filing date: Sep 5, 2000
• Grant date: Sep 16, 2003
• Expiry date: Dec 10, 2021

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/3187
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

There is provided an improve BIST frontend state machine and a method for micro-architectural implementation of the same which is achieved with a minimal amount of test logic circuitry. The state frontend machine includes a state controller responsive to clock signals, control signals, and output register signals for generating output state signals based upon a fixed number of states utilizing death logic so as to sequence through one of a plurality of sets of tests until completed or failed. A substantial savings of approximately 40% in the I.C. chip area was realized in comparison to the implementation by a conventional state machine.