Timing verification method employing dynamic abstraction in core/shell partitioning
US6622290B1 · kind B1 · utility
31Cited by
3References
9Claims
0Family size
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Key dates
| Filing date | Oct 3, 2000 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Dec 21, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for timing verification of very large scale integrated circuits reduces required CPU speed and memory usage. The method involves steps including partitioning the circuit into a plurality of blocks and then partitioning the verification between shell path components and core path components. Timing verification is then conducted for only shell path components while core path components are abstracted or ignored. Finally, timing verification for core path components in each block completes the process for the entire design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.