Method and apparatus for physical budgeting during RTL floorplanning
US6622291B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 30, 2000 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Mar 27, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A feasible floorplan of a circuit is determined and budgeted in the early phases of circuit design. The process of determining the floorplan and budget includes estimating RTL complexity, physical partitioning, block placement, block i/o placement and top level global routing, and verifying feasibility of the floorplan. Allocation of global timing constraints to each block is performed by producing logic cones representing timing of circuit paths in each block. The circuit paths are optimized to determine a feasible timing for each block. The global constraints are allocated proportionally to each block based on the feasible timing for each block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.