Method of determining the time for polishing the surface of an integrated circuit wafer
US6623993B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2001 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | Jul 3, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31053
- WIPO fieldMachine tools
- WIPO sectorMechanical engineering
Abstract
A method of determining the time for polishing the surface of an integrated circuit wafer on a polishing machine. A sample wafer is fabricated to include at least one high plateau and at least one low plateau joined by a sudden transition. At least one initial profile is topographically scanned, and the surface of the sample wafer is polished at a particular polishing pressure for a particular polishing time. The final profile of the polished layer is topographically scanned in the corresponding area, and the initial and final topographical scans of the sample wafer are converted into Fourier series. The surface of the wafer to be polished is topographically scanned, and the topographic scan of the wafer to be polished is converted into a Fourier series. The time for polishing the wafer to be polished is calculated from the Fourier series and the average thickness to be removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.