Ultra small thin windows in floating gate transistors defined by lost nitride spacers
US6624027B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2002 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | May 9, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A tiny tunnel oxide window with dimensions smaller than the minimum feature resolution of the process equipment is formed in an EEPROM structure by placing dummy nitride spacers on either side of a nitride implant mask over a gate oxide layer after source and drain are formed by implantation at opposed sides of the nitride mask. The spacers are formed in a second nitride layer deposit after the nitride mask formation. The spacers are etched to have a desired tunnel oxide dimension. Another oxide layer is deposited over one of the source and drain regions, abutting a nitride spacer. The nitride layers are removed leaving a spacer nest, into which tunnel oxide is deposited. The device is finished in the usual way for an ESPROM structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.