Alignment mark having a protective oxide layer for use with shallow trench isolation
US6624039B1 · kind B1 · utility
9Cited by
9References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2000 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | Sep 3, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a semiconductor device including large topography alignment marks, and a method of manufacture therefor. The method of manufacturing the semiconductor device includes forming an isolation trench and an alignment mark in a substrate to a substantially common depth, and forming an etch stop layer in the alignment mark.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.