Process for annealing semiconductors and/or integrated circuits
US6624052B2 · kind B2 · utility
2Cited by
2References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2002 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | Jul 22, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a semiconductor structure, includes annealing a structure in a deuterium-containing atmosphere. The structure includes (i) a substrate, (ii) a gate dielectric on the substrate, (iii) a gate on the gate dielectric, (iv) an etch-stop layer on the gate, and (v) an interlayer dielectric on the etch-stop layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.