Method for forming high resistance resistor with integrated high voltage device process
US6624079B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2001 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | Sep 21, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/212
Abstract
The method for forming high voltage device combined with a mixed mode process use an un-doped polysilicon layer instead of the conventional polysilicon layer. In the high resistance area, the ion implant is not used until the source region and the drain region are formed. A resistor is formed by etching oxide-nitride-oxide layer and performing ion implant process by using BF2 radical to the un-doped polysilicon layer to control the resistance. Then multitudes of contact are formed, wherein the high dosage of BF2 implant would reduce resistance between contacts and resistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.