Silicon on insulator field effect transistors having shared body contact
US6624459B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2000 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | Apr 12, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Silicon on insulator (SOI) field effect transistors (FET) with a shared body contact, a SRAM cell and array including the SOI FETs and the method of forming the SOI FETs. The SRAM cell has a hybrid SOI/bulk structure wherein the source/drain diffusions do not penetrate to the underlying insulator layer, resulting in a FET in the surface of an SOI layer with a body or substrate contact formed at a shared contact. FETs are formed on SOI silicon islands located on a BOX layer and isolated by shallow trench isolation (STI). NFET islands in the SRAM cells include a body contact to a P-type diffusion in the NFET island. Each NFET in the SRAM cells include at least one shallow source/drain diffusion that is shallower than the island thickness. A path remains under the shallow diffusions between NFET channels and the body contact. The P-type body contact diffusion is a deep diffusion, the full thickness of the island. Bit line diffusions shared by SRAM cells on adjacent wordlines may be deep diffusions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.