Method for fabricating a power semiconductor device having a floating island voltage sustaining layer

US6624494B2 · kind B2 · utility

Assignee

• General Semiconductor, Inc. · US

Inventors

• Richard A. Blanchard · Los Altos, US
• Jean-Michel Guillot · Cloyne, IE

Key dates

• Filing date: Oct 4, 2002
• Grant date: Sep 23, 2003
• Expiry date: Oct 4, 2022

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02E10/548

Abstract

A power semiconductor device and a method of forming the same is provided. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material into a portion of the epitaxial layer adjacent to and beneath the bottom of the trench. The dopant is diffused to form a first doped layer in the epitaxial layer and the barrier material is removed from at least the bottom of the trench. The trench is etched through the first doped layer and a filler material is deposited in the trench to substantially fill the trench, thus completing the voltage sustaining region. At least one region of the second conductivity type is formed over the voltage sustaining region to define a junction therebetween.