Stabilized delay circuit
US6624679B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2001 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | Mar 15, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A delay circuit includes a first inverter connected to a supply voltage, and has an input for receiving an input signal. A delay regulating transistor is connected between the first inverter and a first voltage reference, and has a control terminal for receiving a biasing voltage. A capacitor is connected between an output of the first inverter and the first voltage reference. A second inverter is connected to the output of the first inverter for outputting a delayed output signal. An auxiliary current path is in parallel to the delay regulating transistor for allowing a portion of a discharge current from the capacitor to flow therethrough. The portion of the discharge current is proportional to the supply voltage. The auxiliary current path includes a diode connected to the first inverter, and a second transistor connected between the diode and the first voltage reference. The second transistor has a control terminal for receiving the biasing voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.