Threshold voltage reduction of a transistor connected as a diode
US6624683B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2000 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | Jul 20, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0027
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit design of a transistor connected as a diode, in particular to a design able to reduce the threshold voltage of the transistor and equal to the difference of the threshold voltage of the used transistors in the circuit disposal. The circuit design includes a first pMOS transistor having a second nMOS transistor connected as a diode connected between the gate and the drain of the first transistor and a current generator connected to the gates of the two transistors. Such a circuit design is also applicable to a nMOS transistor. From a general point of view the invention is directed to a nMOS or pMOS transistor whose gate voltage is increased (for the nMOS transistors) or decreased (for the pMOS transistors) by using a circuit in series with the gate that provides an appropriate delta of voltage. 3)
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.