Multiple logical bits per memory cell in a memory device
US6625055B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2002 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | Apr 9, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5692
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read-only memory device is described having non-volatile memory cells that include a memory component connected between electrically conductive traces. A memory component is formed to include a resistor that indicates a resistance value when a potential is applied to a selected memory cell. The resistance value of a memory component in an individual memory cell corresponds to multiple logical bits. The resistance value of a memory component corresponding to a set of logical bits can be based on a thickness and/or an area of electrically resistive material that forms the memory component, and/or based on the geometric shape of the memory component, where different geometric shapes of the electrically resistive material have different resistance values that correspond to different sets of logical bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.