Kenneth J. Eldredge
71Patents
16h-index
34Co-inventors
84Inventor score
Filing activity: Oct 29, 1999 → Dec 6, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6967149B2 | Storage structure with cleaved layer | Electricity | 254 | Expired |
| US6873543B2 | Memory device | Physics | 137 | Expired |
| US6188615A | MRAM device including digital sense amplifiers | Physics | 123 | Expired |
| US6317376A | Reference signal generation for magnetic random access memory devices | Physics | 103 | Expired |
| US6363000B1 | Write circuit for large MRAM arrays | Physics | 93 | Expired |
| US9430735B1 | Neural network in a memory device | Physics | 79 | Active |
| US6534841B1 | Continuous antifuse material in memory structure | Electricity | 71 | Expired |
| US6873544B2 | Triple sample sensing for magnetic random access memory (MRAM) with series diodes | Physics | 62 | Expired |
| US6385111B2 | Reference signal generation for magnetic random access memory devices | Physics | 61 | Expired |
| US6256224A | Write circuit for large MRAM arrays | Physics | 58 | Expired |
| US6262625A | Operational amplifier with digital offset calibration | Electricity | 56 | Expired |
| US6757188B2 | Triple sample sensing for magnetic random access memory (MRAM) with series diodes | Physics | 50 | Expired |
| US6584589B1 | Self-testing of magneto-resistive memory arrays | Physics | 41 | Expired |
| US7877564B2 | Memory configuration and method for calibrating read/write data based on performance characteristics of the memory configuration | Physics | 18 | Active |
| US6839275B2 | Memory system having control circuit configured to receive data, provide encoded received data to match a fault pattern in the array of memory cells | Physics | 18 | Expired |
| US6590850B2 | Packaging for storage devices using electron emissions | Physics | 16 | Expired |
| US6728799B1 | Hybrid data I/O for memory applications | Physics | 10 | Expired |
| US9875799B1 | Methods for pattern matching using multiple cell pairs | Physics | 10 | Active |
| US9965208B1 | Memory device having a controller to enable and disable mode control circuitry of the controller | Physics | 10 | Active |
| US6625055B1 | Multiple logical bits per memory cell in a memory device | Physics | 8 | Expired |
| US6927996B2 | Magnetic memory device | Physics | 7 | Expired |
| US10141055B2 | Methods and apparatus for pattern matching using redundant memory elements | Physics | 7 | Active |
| US9343155B1 | Memory as a programmable logic device | Physics | 7 | Active |
| US6671778B2 | Atomic resolution storage device configured as a redundant array of independent storage devices | Emerging Cross-Sectional Technologies | 6 | Expired |
| US6836429B2 | MRAM having two write conductors | Physics | 6 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.