Method for masking DQ bits
US6625065B2 · kind B2 · utility
6Cited by
1References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2001 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | Oct 16, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for masking DQ bits that are input into a semiconductor memory by a memory controller is described. In this case, the bits to be masked are provided with an increased level and therefore cannot be read into the semiconductor memory due to the increased voltage level which functions as a deactivating voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.