Semiconductor integrated circuit device provided with a self-testing circuit for carrying out an analysis for repair by using a redundant memory cell
US6625072B2 · kind B2 · utility
11Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 23, 2002 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | May 23, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell array is divided into a first and second sub-memory cell arrays. A built-in self-testing circuit is provided with an address replacement determining circuit which is installed in each of the first and second sub-memory cell arrays, and which, assuming that a selection of a memory cell from the first and second sub-memory cell arrays and a replacement thereof to a preliminary memory cell can be carried out mutually in an independent manner, makes a determination as to which preliminary memory cell is used for replacement, and outputs the result of determination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.