Processor for determining physical lane skew order
US6625675B2 · kind B2 · utility
21Cited by
13References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 23, 2001 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | Feb 13, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In parallel-serial architecture based networks that include a transmission media and at least one I/O processor connected to the transmission media by a core, a buffering device is provided that compensates for different latencies from all physical lanes in data links so that data transmission occurs at the same time in the receive path of the I/O “processor.” The processor can be an I/O device for a host channel adapter, a target channel adapter, or an interconnect switch in an InfiniBand-type network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.