Gregory J. Mann
29Patents
7h-index
37Co-inventors
69Inventor score
Filing activity: Sep 21, 1990 → Aug 31, 2015
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5686096A | Medical device for the protection of a catheter penetration site | Human Necessities | 106 | Expired |
| US5322659A | Method for rendering a substrate surface antithrombogenic and/or anti-infective | Performing Operations; Transporting | 27 | Expired |
| US6625675B2 | Processor for determining physical lane skew order | Electricity | 21 | Expired |
| US6665754B2 | Network for increasing transmit link layer core speed | Emerging Cross-Sectional Technologies | 11 | Expired |
| US8222607B2 | Apparatus for time to digital conversion | Physics | 10 | Active |
| US7225387B2 | Multilevel parallel CRC generation and checking circuit | Electricity | 9 | Expired |
| US7890804B2 | Program memory test access collar | Physics | 8 | Active |
| US7308668B2 | Apparatus and method for implementing an integrated circuit IP core library architecture | Physics | 7 | Expired |
| US8866654B2 | Apparatus for analog-to-digital conversion with a high effective-sample-rate on the leading edge of a signal pulse | Electricity | 7 | Active |
| US7941772B2 | Dynamic critical path detector for digital logic circuit paths | Physics | 6 | Active |
| US8786474B1 | Apparatus for programmable metastable ring oscillator period for multiple-hit delay-chain based time-to-digital circuits | Electricity | 6 | Active |
| US7328396B2 | Cyclic redundancy check generating circuit | Electricity | 6 | Expired |
| US8963600B2 | Apparatus for programmable insertion delay to delay chain-based time to digital circuits | Electricity | 5 | Active |
| US7254647B2 | Network for decreasing transmit link layer core speed | Physics | 5 | Expired |
| US7103832B2 | Scalable cyclic redundancy check circuit | Electricity | 4 | Expired |
| US8132136B2 | Dynamic critical path detector for digital logic circuit paths | Physics | 4 | Active |
| US8136010B2 | Apparatus for pipelined cyclic redundancy check circuit with multiple intermediate outputs | Electricity | 3 | Active |
| US7823017B2 | Structure for task based debugger (transaction-event-job-trigger) | Physics | 3 | Active |
| US10758705B2 | Catheter insertion tray with integrated instructions | Human Necessities | 3 | Active |
| US8446308B2 | Apparatus for detection of a leading edge of a photo sensor output signal | Electricity | 3 | Active |
| US7519941B2 | Method of manufacturing integrated circuits using pre-made and pre-qualified exposure masks for selected blocks of circuitry | Physics | 3 | Active |
| US8347019B2 | Structure for hardware assisted bus state transition circuit using content addressable memories | Physics | 3 | Active |
| US7886210B2 | Apparatus for pipelined cyclic redundancy check circuit with multiple intermediate outputs | Electricity | 2 | Active |
| US9063520B2 | Apparatus for inserting delay, nuclear medicine imaging apparatus, method for inserting delay, and method of calibration | Electricity | 2 | Active |
| US7313738B2 | System and method for system-on-chip interconnect verification | Physics | 1 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.