Method apparatus, and system for efficient address and data protocol for a memory
US6625716B2 · kind B2 · utility
10Cited by
4References
31Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 28, 2001 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | Jan 11, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory to support an Address-Data Multiplexed protocol in response to a substantially simultaneous assertion of RAS and CAS, and an Address—Address Multiplexed protocol in response to an assertion of RAS followed by an assertion of CAS.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.