Microprocessor instruction buffer redundancy scheme
US6625746B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 15, 2000 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | Dec 25, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is a mechanism for providing redundancy in the instruction buffer of a microprocessor such individual entries which test bad during manufacturing can be tolerated and the baseline specification of the microprocessor can be met. The present invention utilizes the instruction allocation logic of a microprocessor to allow additional buffer entries, above those called for in the specification to be provided. More particularly, each buffer entry is tested and the results are used to identify which individual entry or entries have a defective operational status. This information is then used to update the instruction allocation logic such that functional entries are considered for allocation, while those entries that test bad can be avoided. Further, the test status information can be used to set a “manufactured good” bit in the entry itself. This bit is then read ultimately by the allocation logic and instructions can be allocated accordingly, i.e. only to those entries which have tested good.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.