Charles Roberts Moore
22Patents
15h-index
16Co-inventors
70Inventor score
Filing activity: Oct 9, 1992 → Dec 15, 2000
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5724565A | Method and system for processing first and second sets of instructions by first and second types of processing systems | Physics | 139 | Expired |
| US6728866B1 | Partitioned issue queue and allocation strategy | Physics | 99 | Expired |
| US5611058A | System and method for transferring information between multiple buses | Physics | 93 | Expired |
| US5437017A | Method and system for maintaining translation lookaside buffer coherency in a multiprocessor data processing system | Physics | 73 | Expired |
| US6766442B1 | Processor and method that predict condition register-dependent conditional branch instructions utilizing a potentially stale condition register value | Physics | 42 | Expired |
| US5706464A | Method and system for achieving atomic memory references in a multilevel cache data processing system | Physics | 40 | Expired |
| US6662294B1 | Converting short branches to predicated instructions | Physics | 31 | Expired |
| US6609190B1 | Microprocessor with primary and secondary issue queue | Physics | 30 | Expired |
| US5442766A | Method and system for distributed instruction address translation in a multiscalar data processing system | Physics | 29 | Expired |
| US6654869B1 | Assigning a group tag to an instruction group wherein the group tag is recorded in the completion table along with a single instruction address for the group to facilitate in exception handling | Physics | 25 | Expired |
| US5500950A | Data processor with speculative data transfer and address-free retry | Physics | 24 | Expired |
| US6725354B1 | Shared execution unit in a dual core processor | Physics | 24 | Expired |
| US6748519B1 | Method and apparatus for utilizing renamed registers based upon a functional or defective operational status of the register | Physics | 23 | Expired |
| US6678820B1 | Processor and method for separately predicting conditional branches dependent on lock acquisition | Physics | 20 | Expired |
| US5848283A | Method and system for efficient maintenance of data coherency in a multiprocessor system utilizing cache synchronization | Physics | 15 | Expired |
| US6625746B1 | Microprocessor instruction buffer redundancy scheme | Physics | 14 | Expired |
| US6938148B2 | Managing load and store operations using a storage management unit with data flow architecture | Physics | 8 | Expired |
| US6658555B1 | Determining successful completion of an instruction by comparing the number of pending instruction cycles with a number based on the number of stages in the pipeline | Physics | 5 | Expired |
| US6658558B1 | Branch prediction circuit selector with instruction context related condition type determining | Physics | 5 | Expired |
| US5603057A | System for initiating data transfer between input/output devices having separate address spaces in accordance with initializing information in two address packages | Physics | 3 | Expired |
| US5692218A | System for transferring data between input/output devices having separate address spaces in accordance with initializing information in address packages | Physics | 1 | Expired |
| US5793986A | Method and system for enhanced efficiency of data transfers from memory to multiple processors in a data processing system | Physics | 1 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.