Means and method for compiling high level software languages into algorithmically equivalent hardware representations
US6625797B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2000 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | Feb 10, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The compilation of a high-level software-based description of an algorithm into efficient digital hardware implementation(s) is addressed. This is done through the definition of new semantics for software constructs with respect to hardware implementations. This approach allows a designer to work at a high level of abstraction, while the semantic model can be used to infer the resulting hardware implementation. These semantics are interpreted through the use of a compilation tool that analyzes the software description to generate a control and data flow graph. This graph is then the intermediate format used for optimizations, transformations and annotations. The resulting graph is then translated to either a register transfer level or a netlist-level description of the hardware implementation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.