Method of manufacturing a vertical metal connection in an integrated circuit
US6627093B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2000 |
| Grant date | Sep 30, 2003 |
| Priority date | — |
| Expiry date | Oct 12, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
At least one layer of a dielectric material 3 is deposited on a copper track 1 covered with an encapsulation layer 2. A cavity 6 is etched in the layer of dielectric material at the location of the future vertical connection. At least one protective layer is deposited in said cavity to preclude diffusion of copper 7. The protective layer 7 at the bottom of the cavity 6 is subjected to an anisotropic etching treatment and also the encapsulation layer 2 is subjected to etching, whereafter the cavity is filled with copper. The copper particles pulverized during etching the encapsulation layer do not contaminate the dielectric material 3.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.