Semiconductor device manufacturing method
US6627554B1 · kind B1 · utility
15Cited by
14References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 27, 2000 |
| Grant date | Sep 30, 2003 |
| Priority date | — |
| Expiry date | Mar 27, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76832
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device manufacturing method having a multi-layered wiring structure comprises the steps of forming an insulating film over a semiconductor substrate, coating resist on the insulating film, forming a wiring pattern window in the resist, forming a wiring recess by etching the insulating film via the window, removing the resist, removing a reaction product existing on the insulating film by exposing the insulating film to a plasma atmosphere using an inactive gas, and burying a metal film into the wiring recess to form a wiring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.