Method of designing and structure for visual and electrical test of semiconductor devices
US6627926B2 · kind B2 · utility
7Cited by
15References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2001 |
| Grant date | Sep 30, 2003 |
| Priority date | — |
| Expiry date | Aug 26, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/926
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a semiconductor device using fill shape patterns incorporated into wiring levels to increase the planarity of the wiring levels, the fill shapes are aligned from one wiring level to another wiring level to provide lines of sight to lower wiring levels for visual inspection. Also, in accordance with the invention, selected aligned fill shapes are interconnected with vias to form conductive stacks for contacting lower wiring level conductive wires from upper wiring levels in order to perform electrical test probing/diagnostics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.