Structure and method of MOS transistor having increased substrate resistance
US6627955B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2002 |
| Grant date | Sep 30, 2003 |
| Priority date | — |
| Expiry date | Jan 14, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structure and fabrication method of a lateral MOS transistor, positioned on the surface of an integrated circuit fabricated in a semiconductor of a first conductivity type, comprising a source and a drain, each having at the surface a region of the opposite conductivity type extending to the centrally located gate, defining the active area of said transistor; and a semiconductor region within said semiconductor of the first conductivity type, having a resistivity higher than the remainder of the semiconductor, this region extending vertically below the transistor while laterally limited to the area of the transistor such that the resistivity under the gate is different from the resistivity under the source and drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.