Techniques for maintaining parallelism between optical and chip sub-assemblies

US6628000B1 · kind B1 · utility

Assignee

• NATIONAL SEMICONDUCTOR CORPORATION · US

Inventors

• Ken Pham · San Jose, US
• Jia Liu · Wuxi, CN
• Luu Thanh Nguyen · San Jose, US
• William Paul Mazotti · San Martin, US
• Bruce Carlton Roberts · San Jose, US

Key dates

• Filing date: Nov 19, 2001
• Grant date: Sep 30, 2003
• Expiry date: Feb 23, 2022

Classification

• Technology area (CPC G): Physics
• CPC primary: G02B6/4232
• WIPO field: Optics
• WIPO sector: Instruments

Abstract

Techniques for maintaining the optical coupling efficiency between photonic devices of an optoelectronic module and its interconnecting optical fibers are described. The techniques ensure that the mating surfaces of an optical sub-assembly and a chip sub-assembly remain planar to each other throughout and after the soldering process of the optoelectronic manufacturing process. These techniques include the use of a ceramic fixture made of a stack of plates having openings that secure the orientation of the optical and chip sub-assemblies. The fixture can have one or more openings to secure a respective one or more combination of optical and chip sub-assemblies. A high temperature tape can also be used to maintain the parallelism between the optical and chip sub-assemblies. An optical sub-assembly having pedestals on its bottom surface can also be use to maintain parallelism of the optical and chip sub-assemblies. Methods of using each technique is also described.