Memory module including module data wirings available as a memory access data bus
US6628538B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2002 |
| Grant date | Sep 30, 2003 |
| Priority date | — |
| Expiry date | Mar 26, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A module substrate has a plurality of module data terminal pairs individually provided in association with respective chip data terminals in a plurality of memory chips, and a plurality of module data wirings which respectively connect between the plurality of module data terminal pairs. The plurality of module data wirings are connected to their corresponding chip data terminals and are configured so as to be available as a memory access data bus. In a memory system in which a plurality of memory modules are arranged in parallel, module data wirings of each individual memory modules are connected in serial form, and each individual module data wirings do not constitute branch wirings with respect to a data bus on a motherboard of the memory system. In the memory modules, parallel access for the number of bits corresponding to the width of the memory access data bus is assured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.